About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Job Posting Title: Staff RTL Design Engineer (FuSa/RAS)

The Role:

As a FuSa/RAS design engineer at SiFive, you will be contributing to an overall FuSa/RAS solution portfolio that is seamless, coherent and extensible, whilst extending it across a widely configurable RISC-V IP and unique development environment. We are looking for people who are as excited as we are about working in a dynamic, collaborative environment to bring new and innovative hardware IP to market quickly - the smart way.

Responsibilities:

• Architect, design and implement in Chisel new Fusa/RAS features for RISC-V CPU core generators.

• Support the FuSa/RAS architects in performing the required safety analysis and deriving the set of requirements to enable the SiFive IP Portfolio to detect failures, report them and enable smarter reactions.

• Perform initial verification and work with the design verification team to create and execute thorough verification test plans.

• Work with the physical implementation team to implement and optimise physical design to meet frequency, area, power and functional safety goals.

• Create documentation (including functional safety documentation) to a high standard and collaborate across teams and disciplines.
  

Requirements:

• Masters or higher degree in Electronic Engineering or Computer Science OR a degree in a related field with a strong background in code development.

• 5+ years of RTL design or related design experience.

• Academic or professional experience with CPU RTL design in Chisel, Verilog, System Verilog or VHDL.

• Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware generator design.

• Attention to detail and a focus on high-quality code and documentation.

• Ability to work well with others and share the belief that engineering is teamwork.

Nice to have:

• Experience with Scala and/or Chisel is a plus.

• Experience with Functional Safety and/or RAS design is a plus.

• Knowledge of verification principles, formal or UVM testbenches is a plus.

• Knowledge of RISC-V architecture.

Location:

• Preferably Cambridge (hybrid)

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.